This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. P2000-312015 filed on Oct. 12, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, to a method of reforming contacts that connect a semiconductor substrate to wiring in a semiconductor device and refining films such as silicide films and silicon nitride films formed on the semiconductor substrate. The present invention also relates to the semiconductor device itself manufactured or reformed by the method.
2. Description of the Related Art
Large-scale integrated circuits (LSIs) including many elements such as transistors, resistors, and capacitors are widely installed for computers and communication devices. The performance of the device is dependent on the performance of the installed LSI, and the performance of the LSI is dependent on the degree of integration of elements in the LSI. The degree of integration of the LSI improves if the size of element of the LSI is reduced, and the element size reduces if the influence of heat treatment during manufacturing is minimized. The heat treatment causes unexpected damage on semiconductor elements and deteriorates the properties thereof. Various heat treatments are carried out during semiconductor device manufacturing, to improve connecting between contacts formed in an insulating film and a silicide layer formed on a semiconductor substrate, to form a silicide layer on gate electrodes and source/drain regions, to refine a silicon nitride film formed on DRAM gate electrodes, or to reform a metal silicide layer serving as EEPROM gate electrodes.
To property connect the bottom of a contact formed in an interlayer insulating film to a semiconductor substrate, a titanium (Ti) film is formed on the inner surface of a contact hole by spattering and a heat treatment is carried out to reduce a natural oxide film formed on the substrate and form a silicide layer in a source/drain region of the substrate below the Ti film. The spattering used to form the Ti film is an improper technique to completely fill very fine contact with high aspect rate, e.g., 0.1 -xcexcm-generation with a tungsten film serving as a contact conductor. On the other hand, the Ti film is unable to form by thermal CVD (chemical vapor deposition), although there is a thermal CVD technique to properly form a TiN film in such fine contact holes. The TiN film, however, is not allowed to directly coat contact holes because conventional heat treatment for the TiN film is unable to reduce a natural oxide film formed on a substrate. According to the 0.1-xcexcm-generation contact holes, the silicide layer formed in the source/drain region below the Ti film is too close to a junction between the source/drain region and the substrate, because the source/drain region of the 0.1-xcexcm-generation is very shallow. This results in increasing a junction leakage current. The silicide layer formed below the contact wire will be unnecessary if the natural oxide film formed between the contact and silicide layer can be reduced (deoxidized) without using the Ti film. This is because the surface of the source/drain region is usually provided with a metal silicide layer such as a cobalt silicide layer that secures low resistance between the contact and the source/drain region if there is no interfering natural oxide film. However, reducing the natural oxide film without using the Ti film is nearly impossible to achieve because triggering a reaction between the TiN film and the substrate to reduce the natural oxide film needs a high-temperature heating process that surely deteriorates the impurity profile of the source/drain region.
Recent MOS transistors employ a metal silicide layer to reduce parasitic resistance. The metal silicide layer is formed on a diffusion layer through first and second heating processes. The first heating process makes a metal film react with a silicon semiconductor substrate and forms a metal monosilicide layer. After removing unreacted part of the metal film, the second heating process changes the metal monosilicide into metal disilicide. If the metal is cobalt (Co), the second heating process causes a small amount of Co atoms to diffuse into the substrate. The Co atoms form a deep level in Si and approach a junction between the diffusion layer and the substrate under the metal disilicide (CoSi2) layer. These Co atoms around the junction increase a junction leakage current. It is necessary, therefore, to keep the CoSi2 layer away from the junction by a distance of 100 to 150 nanometers (nm). As the size of each transistor because smaller, the diffusion layer becomes shallower to make it difficult to keep a proper distance between the metal disilicide layer and the junction.
To manufacture LSIs, it is imperative to form a silicon nitride (SiN) film that effectively functions as an etching stopper, a barrier, or an insulator. The SiN film made by chemical reaction between silicon source and ammonia contains hydrogen, and that made by chemical reaction between dichlorosilane or hexachlorosilane and ammonia contains hydrogen.
The SiN film containing hydrogen must be dehydrogenated through a high-temperature post-heat treatment. If the SiN film is formed on PMOS elements containing boron, the hydrogen removed from the SiN film causes the boron in the PMOS elements to rapidly diffuse. The post-heat treatment carried out on the SiN film may be activation annealing that is carried out at 900xc2x0 C. or higher with a rapid thermal annealing apparatus. This annealing diffuses boron contained in the PMOS elements into a semiconductor substrate through a gate insulating film. The boron diffused to the substrate greatly changes the impurity profile of the substrate, thereby changing the threshold voltage of each PMOS transistor. The punch-through of the gate insulating film by boron atoms unevenly occurs over the substrate, and therefore, the threshold voltages of PMOS transistors vary over the substrate. At the same time, the gate electrode of each transistor is depleted. In this way, the high-temperature post-heat treatment on the SiN film on PMOS elements containing boron causes the punch-through of a gate insulating film by boron atoms, to drastically deteriorate the properties of the elements. Namely, the punch-through by boron atoms causes the problems of (1) changing the impurity profile of a semiconductor substrate to change the threshold voltages of transistors, (2) varying the transistor threshold voltages over the substrate, and (3) depleting the electrodes of the transistors.
The punch-through problem by boron atoms will be severer in the next-generation semiconductor elements that are more integrated with thinner gate insulating films and finer semiconductor elements. The quantity of boron atoms passing through a gate insulating film increases as the film becomes thinner and as the quantity of boron atoms used to decrease electrode resistance becomes larger. To improve the performance of a transistor, a diffusion layer where the transistor is formed must be shallow. The shallow diffusion layer is vulnerable to the boron atoms passed through a gate insulating film. In this way, using the hydrogen-containing SiN film for the next-generation semiconductor elements severely deteriorates the properties of semiconductor elements. To solve these problems, it is required to provide a technique of employing a hydrogen-reduced SiN film or a technique of carrying out dehydrogenation on a SiN film without deteriorating the properties of semiconductor elements.
A flash memory has control gate electrodes each consisting of a multilayered structure of polysilicon and tungsten silicide (WSi) films. The WSi film has high resistance, and therefore, must be processed through high-temperature post-heat treatment to reduce the resistance. This post-heat treatment must be carried out at 1000xc2x0 C. or higher. This high temperature deteriorates the properties of gate oxide and nitride films. It is required, therefore, to provide a technique of reducing the resistance of a WSi film without deteriorating the properties of semiconductor elements.
A method of manufacturing a semiconductor device according to an embodiment of the present invention including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600xc2x0 C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
A semiconductor device according to an embodiment of the present invention including, a semiconductor substrate, source/drain regions formed at the surface of the substrate, a polysilicon electrode formed on a gate insulating film that is formed on the substrate between the source/drain regions, and a metal silicide layer formed on the gate electrode and source/drain regions, a distance between the bottom of the metal silicide layer on the source/drain regions and a junction between the bottom of the source/drain regions and the substrate is shorter than 100 nm.